package XunChunCPU.common.Bundles

import chisel3._
import XunChunCPU.common.CommonConfig._

class RegReadBundle extends Bundle {
    val rsAddr = Input(UInt(regAddrLen.W))
    val rtAddr = Input(UInt(regAddrLen.W))
    val rsData = Output(UInt(regLen.W))
    val rtData = Output(UInt(regLen.W))
}